1. Field of the Invention
The invention relates in general to a PCI (Peripheral Component Interconnect) Express system and a method of transitioning a power state thereof, and more particularly to a PCI Express system and a method of transitioning a link state (L-state) thereof.
2. Description of the Related Art
PCI (Peripheral Component Interconnect) interfaces are originally the mainstream of personal computers. With the progress of time, however, a higher transmission bandwidth required in future processors and output/input components has greatly exceeded the range of the PCI interface. A new generation of PCI Express has been disclosed to serve as the standard local input/output bus for various operation platforms. The maximum features include the enhancement of efficiency and the high one-way transmission rate of 2.5 GHz. Furthermore, the transmission rate can be increased as the number of lanes increases. For example, the transmission rate can be increased by four times when four lanes are used.
The ACPI (Advanced Configuration and Power Interface) defines the power state of the component in various states and is referred to as D-state (Device State). The PCI Express further defines the power state of a link between components, which is referred to as L-state (Link State). Each L-state and each D-state have a corresponding relationship.
The D0 state (Full-On) represents that the component is under a normal working state. When the component is under the D0 state, the link between the components is under the L0, L0s or L1 states.
The D1 state and D2 state are not obviously defined in ACPI. In general, the D2 state saves more power than the D0 and D1 states, but can hold the states of fewer components. The D1 state consumes more power than the D2 state, but can hold the states of more components. The D1 and D2 states correspond to the L1 state.
The D3 state (Off) represents a shutdown state and includes D3cold and D3hot states. When the components are under the D3cold state, it means that the main power is not supplied to the components. When the components are in the D3hot state, it means that the main power is supplied to the components. When the power states of the components are under the D3cold state, the links between the components correspond to the L2 state if an auxiliary power is supplied to the components; and the links between the components correspond to the L3 state if no power is supplied to the components. The D3hot state corresponds to the L1 state.
The L0 state represents that the power states of the links between the components are under the normal working state. When data is transmitted on the links between the components, if a short idle represented, the link can be entered to L0s state to decrease the power consumption.
When the links between the components are under the L1 state, the components have no working request, and the power requirement of the links between the components is decreased. At this time, the clock signal doesn't trigger, and the PLL (Phase Locked Loop) also pauses.
The L2 state and L3 state are the shutdown states. An auxiliary power exists under the L2 state, and no auxiliary power exists under the L3 state.
However, it is found that the power consumption can't be save due to the L0s state cannot be properly entered or entered more frequently from L0 state, and thus the object of power-saving cannot be really achieved.